ARM920T clocking

The ARM920T has two functional clock inputs, BCLK and FCLK. Internally, the ARM920T is clocked by GCLK,which can be seen on the CPCLK output as shown in Figure 5-1.GCLK can be sourced from either BCLK or FCLK depending on the clocking mode, selected using nF bit and iA bit in CP15 register 1 (see Register 1: Control register on page 2-12),and external memory access.The three clocking modes are FastBus, synchronous and asynchronous.

ARM920T有2個時鐘輸入，分別是BCLK和FCLK。從圖5－1中GPCLK的輸出可以看出，ARM920T內部是由GCLK時鐘模式驅動。CP15寄存器1（參見寄存器1：控制寄存器，2－12頁）的nF位和iA位決定時鐘模式，即決定了GCLK是由FCLK還是BCLK產(chǎn)生。一共有3種時鐘模式，分別為快速總線、同步以及異步模式。

The ARM920T is a static design and both clocks can be stopped indefinitely without loss of state. From Figure 5-1 it can be seen that some of the ARM920T macrocell signals will have timing specified with relation to GCLK, which can be either FCLK or BCLK depending on the clocking mode

ARM920T的設計是固定的，兩種時鐘都可以被無期限的暫停，而不會導致狀態(tài)丟失。從圖5－1這可以看出，有些ARM92的macrocell信號的timing受到GCLK的影響，而GCLK具體是由FCLK是還是BCLK產(chǎn)生，則是由時鐘模式?jīng)Q定。

FASTBUS MODE

快速總線模式

In FastBus mode GCLK is sourced from BCLK. The FCLK input is ignored. This

means that BCLK is used to control the AMBA ASB interface and the internal

ARM920T processor core.

On reset, the ARM920T is put into FastBus mode and operates using BCLK. A typical

use for FastBus mode is to execute startup code while configuring a PLL under software

control to produce FCLK at a higher frequency. When the PLL has stabilized and

locked, you can switch the ARM920T to synchronous or asynchronous clocking using

FCLK for normal operation.

在快速總線模式，GCLK來自于BCLK，F(xiàn)CLK輸入被忽略。這意味著BCLK被用來控制AMBA ASB接口和內部的ARM920T處理器核。復位時，ARM920T進入快速總線模式，操作使用BCLK。一般快速總線模式在啟動代碼時執(zhí)行，然后由軟件配置PLL產(chǎn)生高頻的FCLK。在PLL穩(wěn)定后可以切換ARM920T到同步或異步時鐘，使用FCLK進行操作。

小結:

• GCLK＝BCLK，F(xiàn)CLK被忽略

• 板子reset之后即進入該模式

• 該模式的典型應用是執(zhí)行啟動代碼，同時軟件配置PLL，使得FCLK更高

• nF=0且iA=0

SYNCHRONOUS MODE

同步模式

In this mode of operation GCLK is sourced from BCLK or FCLK. There are three

restrictions that apply to BCLK and FCLK:

? FCLK must have a higher frequency than BCLK

? FCLK must be an integer multiple of the BCLK frequency

? FCLK must be HIGH whenever there is a BCLK transition.

在這個操作模式GCLK來自于BCLK或FCLK。但是對于BCLK和FCLK要滿足3個條件：

1.FCLK必須比BCLK有更高的頻率

2.FCLK必須是BCLK頻率的整數(shù)倍數(shù)

3. 無論BCLK怎么轉換，F(xiàn)CLK的頻率都要高于BCLK

BCLK is used to control the AMBA ASB interface, and FCLK is used to control the

internal ARM920T processor core. When an external memory access is required the

core either continues to clock using FCLK or is switched to BCLK, as shown in

Table 5-1. This is the same as for asynchronous mode.

BCLK被用來控制AMBA ASB總線接口，F(xiàn)CLK用來控制內部的ARM920T處理器核。

• 當訪問外部存儲地址時，處理器核心要么繼續(xù)使用FCLK，要么切換到BCLK。見表1。

表1

The penalty in switching from FCLK to BCLK and from BCLK to FCLK is

symmetric, from zero to one phase of the clock to which the core is re-synchronizing.

That is, switching from FCLK to BCLK has a penalty of between zero and one BCLK

phase, and switching back from BCLK to FCLK has a penalty of between zero and one

FCLK phase.

從FCLK切換到BCLK與BCLK切換到FCLK的代價是相等的。需要耗費0～1個時鐘周期使核重新同步。從FCLK切換到BCLK的代價是0～1個BCLK。從BCLK切換到FCLK的代價是0～1個FCLK。

Figure 5-2 on page 5-5 shows an example zero BCLK phase delay when switching

from FCLK to BCLK in synchronous mode.

Figure 5-2 Synchronous mode FCLK to BCLK zero phase delay

Figure 5-3 shows an example one BCLK phase delay when switching from FCLK to

BCLK in synchronous mode.

Figure 5-3 Synchronous mode FCLK to BCLK one phase delay

小結：

• GCLK＝BCLK或者GCLK＝FCLK
• FCLK＝n*BCLK(n大于1且為整數(shù))
• BCLK用于控制AMBA ASB接口，而FCLK用來控制內部的ARM920T處理器核心。當訪問外部存儲地址時，處理器核心要么繼續(xù)使用FCLK，要么切換到BCLK。見表1。
• nF=1且iA=0

Asynchronous mode

異步模式

In this mode of operation GCLK is sourced from BCLK or FCLK. FCLK and BCLK

can be completely asynchronous to one another, with the one restriction that FCLK

must have a higher frequency than BCLK.

BCLK is used to control the AMBA ASB interface, and FCLK is used to control the

internal ARM920T processor core. When an external memory access is required the

core either continues to clock using FCLK or is switched to BCLK. This is the same

as for synchronous mode.The penalty in switching from FCLK to BCLK and from

BCLK to FCLK is symmetric, from zero to one cycle of the clock to which the core is

re-synchronizing. That is, switching from FCLK to BCLK has a penalty of between

zero and one BCLK cycle, and switching back from BCLK to FCLK has a penalty of

between zero and one FCLK cycle.

在這個操作模式GCLK來自于BCLK或FCLK。FCLK和BCLK之間可以完全異步，只有一個要滿足的條件是FCLK的頻率要高于BCLK。BCLK被用來控制AMBA ASB總線接口，F(xiàn)CLK用來控制內部的ARM920T處理器核。與同步模式時相同，從FCLK切換到BCLK與BCLK切換到FCLK的代價是相等的。需要耗費0～1個時鐘周期使核重新同步。從FCLK切換到BCLK的代價是0～1個BCLK。從BCLK切換到FCLK的代價是0～1個FCLK。

Figure 5-4 shows an example zero BCLK cycle delay when switching from FCLK to

BCLK in asynchronous mode.

Figure 5-4 Asynchronous mode FCLK to BCLK zero cycle delay

Figure 5-5 on page 5-7 shows an example one BCLK cycle delay when switching from

FCLK to BCLK in asynchronous mode.

Figure 5-5 Asynchronous mode FCLK to BCLK one cycle delay

小結：

• GCLK＝BCLK或者GCLK=FCLK
• BCLK用于控制AMBA ASB接口，而FCLK用來控制內部ARM920T處理器核心。當訪問外部存儲地址時，處理器核心要么繼續(xù)使用FCLK，要么切換到BCLK。見表1。
• nF=1且iA=1